The present invention relates generally to the field of clearing a cache, and more particularly to non-disruptive clearing of varying address ranges from a cache.
A cache is a component that transparently retains data elements (or simply data) so that future requests for any retained data can be served faster. A data element that is stored within a cache corresponds to a pre-defined storage location within a computer memory system. Such a data element might be a value that has recently been computed or a duplicate copy of the same data element that is also stored elsewhere.
When multiple images are stored in computer systems, it is highly desirable to dynamically reallocate storage among the multiple images in order to increase storage sizes for images which need improved throughput. Therefore, it is necessary to clear cache entries which correspond to respective storage addresses being reallocated from existing images and into critical images. Typically, the storage addresses being reallocated include a large contiguous range of storage addresses. The clearing of cache entries containing storage addresses being reallocated requires a full quiesce of the system, therefore, it needs to be performed quickly to minimize any impact on the system performance.
Many system state changes, such as data storage reallocation, require a conventional quiesce to pause all processors in the system. One processor requests quiesce of the system, which means that all processors need to pause what they are doing and indicate that they will pause all operations until further notice. Once all processors pause and respond, the system state change can occur. Once completed, the requesting processor will send a “reset quiesce” broadcast to all processors to resume their operations.